1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to structures and methods for improving the reliability of non-volatile memory devices.
2. Description of the Related Art
Non-volatile memory devices are in widespread use in many modern integrated circuit devices and in many consumer products. In general, memory devices are the means by which electrical information is stored. FIG. 1 depicts one illustrative example of a prior art memory device 100. In general, the memory device 100 includes a gate insulation layer 20 (sometimes referred to as a “tunnel oxide”), a charge storage layer 22, a blocking insulation layer 24, a gate electrode 26, spacers 28, and illustrative source/drain regions 30. The illustrative memory device 100 is formed in and above the active layer 10C of the semiconducting substrate 10. An illustrative isolation structure 12, e.g., a shallow trench isolation structure, that is formed in the substrate 10 to electrically isolate the memory device 100 from other adjacent devices is also depicted. In one illustrative embodiment, the semiconducting substrate 10 a silicon-on-insulator (SOI) substrate comprised of bulk silicon 10A, a buried insulation layer 10B (commonly referred to as a “BOX” layer) and an active layer 10C, which may also be a silicon material. The various structures depicted in FIG. 1 may be made from a variety of material. In one typical configuration that is commonly employed the gate insulation layer 20 and the blocking insulation layer 24 are made of silicon dioxide, the charge storage layer 22 is made of silicon nitride, and the gate electrode 26 is made of polysilicon. This is sometimes referred to as an “ONO” type memory device because of the materials employed (Oxide-Nitride-Oxide). In another common configuration the gate insulation layer 20 and the blocking insulation layer 24 are made of silicon dioxide, while the charge storage layer 22 and the gate electrode 26 is made of polysilicon. This is sometimes referred to as a “floating gate” type memory device.
Millions of such memory devices 100 are typically included in even very basic electronic consumer products. Irrespective of the type of memory device, there is a constant drive in the industry to increase the performance and durability of such memory devices. In typical operations, an electrical charge is stored on the charge storage layer 22 to represent a digital “1” while the absence of such an electrical charge on the charge storage layer 22 indicates a digital “0”. Special read/write circuitry is used to access the memory device to store information on such a memory device and to determine whether or not a charge is present on the charge storage layer 22 of the memory device. These program/erase cycles (“P/E cycles”) typically occur millions of times for a single memory device 100 over its effective lifetime.
Unfortunately, a large number of P/E cycles can cause damage to the device 100, such as damage to the gate insulation layer 20, and limit the useful life of the device 100. For example, over time, such P/E cycles can cause the access time of the memory device to increase thereby making the memory device slower to use. As a result the system or device that includes the memory device may operate at a slower overall speed. Another problem with such memory devices is a result of process induced defects. The manufacture of the memory device involves many complex manufacturing steps that include oxidation processes, heating processes, etching processes, deposition process, etc., that are performed in a detailed sequence in order to make the device. Some of these process operations are performed at elevated temperatures and expose parts of the device to very harsh environments. One example of a process induced defect is the stress induced in one or more of the layers that make up the memory device 100 when the device is subjected to various etching process. Another example of a process induced defect is the damage to the gate insulation layer 20 that may occur during ion implantation processes, like so-called HALO implant processes. Both process induced defects and P/E cycle induce defects can cause problems such as slowing the operation speed of the memory device 100 and reducing its ability to hold an electrical charge on the charge storage layer 22.
The channel length 100L of the memory device 100 has greatly decreased over the years. For example, in current-day memory devices, the channel length 100L may be on the order of 0.3-0.8 μm, and there is a constant drive to reduce this gate length even further. In general, the operation of the memory device 100 involves applying a voltage to the gate electrode 26 so as to set up an electrical field that established an inversion layer in the substrate under the gate insulation layer 20. Once this inversion layer is established, electrons may flow from the source region to the drain region. Unfortunately, this electrical field is not uniform across the device in the gate length direction (from left to right when viewing FIG. 1A). FIG. 1B is a cross sectional view of the device 100 wherein only the basic gate structure is depicted so as to discuss various aspects of this non-uniform electrical field that is established for the device 100 during operations. As shown in FIG. 1B, the highest magnitude or peak value 100p of the electrical field 100e is typically present near the outer edge of the gate insulation layer 20. Due to the presence of the peak value 100p of the electrical field 100e near the edge of the gate insulation layer 20, it is the outer edge(s) of the gate insulation layer 20 that are mostly likely to be damaged during repeated P/E cycles. Efforts have been made to lower the magnitude of peak value 100p of the electrical field 100e to address such problems but such a solution typically results in the device 100 that exhibits poor programming speeds. Various implantation techniques have been used to move or shift the location of the peak value 100p of the electrical field 100e away from the edge region of the gate insulation layer 20. For example, in some devices the distance between the extension regions 30A of the source/drain regions 30 has been decreased (by increasing dopant dosage) in an effort to shift the location of the peak value 100p of the electrical field 100e more toward the center of the gate insulation layer 20, but such a “solution” produces a device where it is very difficult to control the so-called short channel effects. In other devices, the distance between the extension regions 30A of the source/drain regions 30 has been increased (by decreasing dopant dosage) in an effort to shift the location of the peak value 100p of the electrical field 100e outwardly (in a direction toward the source/drain regions) and away from the gate insulation layer 20, but such a “solution” produces a device that exhibits poor programming speeds.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.